Many ICs today, each of which integrates into one chip many transistors and resistors connected in such a manner as to configure an electric circuit, are used in the important parts of computers and communication equipments. The ICs that include a power semiconductor device are designated as the “power ICs”.
The IGBT is a power device that facilitates realizing both the high-speed switching performance and capability of being driven with a voltage of the MOSFET, and the low ON-voltage characteristics of the bipolar transistor. The IGBT is used in the industrial apparatuses such as a general purpose inverter, an AC servo, an uninterruptible power source (hereinafter referred to as a “UPS”), and a switching power supply. The IGBT has been expanding the application fields thereof to the civil instruments such as an electronic oven, a rise cocker, and a stroboscope. Developments of the IGBTs of the next generation have been explored vigorously. Based on the development of a new IGBT employing a new chip structure and exhibiting a lower ON-voltage, the power loss of the apparatus, to which the new IGBT is applied, is reduced and the efficiency thereof is improved.
The structures of the IGBTs may be classified mainly into a punch-through-type IGBT (hereinafter referred to as a “PT-type IGBT”), a non-punch-through-type IGBT (hereinafter referred to as an “NPT-type IGBT”), and a field-stop-type IGBT (hereinafter referred to as an “FS-type IGBT”). Excluding p-channel-type IGBTs used for audio power amplifiers, almost all the IGBTs mass-produced these days are n-channel-type ones having a vertical double-diffusion structure. In the following descriptions, the IGBT will be an n-type IGBT, if not specifically described otherwise. Further, in the following descriptions, electrons or holes are majority carriers in the semiconductor prefixed with “n-type” or “p-type”. The symbol “+” or “−” on the shoulder of the letter “n” or “p” indicating the conductivity type of the semiconductor indicates that the semiconductor is doped relatively heavily or relatively lightly.
The PT-type IGBT includes an n+-type layer (n-type buffer layer) between a p+-type epitaxial substrate and an n−-type layer (n-type active layer) such that the depletion layer in the n-type active layer reaches the n-type buffer layer. This structure is the mainstream of the fundamental structure for the IGBTs. It is thick enough for the n-type active layer in the IGBT of the 600 V breakdown voltage class to be around 70 μm. However, if the p+-type epitaxial substrate is included, the total thickness will be from 200 μm to 300 μm. In order to overcome this problem, the NPT-type IGBT and the FS-type IGBT have been developed. The NPT-type IGBT and the FS-type IGBT form therein a shallow p+-type collector layer, the dose amount thereof is low, by employing a floating-zone substrate (hereinafter referred to as an “FZ substrate” formed by the floating zone method (hereinafter referred to as the “FZ method”) in substitution for the epitaxial substrate for reducing the thickness and the manufacturing costs thereof.
FIG. 11 is a cross sectional view of an NPT-type IGBT. NPT-type IGBT 100 shown in FIG. 11 includes n−-type FZ substrate (hereinafter referred to as “FZ-N substrate”) 1, gate oxide film 4 of SiO2 and such an oxide on FZ-N substrate 1, gate electrode 5 on gate oxide film 4, interlayer insulator film 7 of boro-phospho silicate glass (hereinafter referred to as “BPSG”) on gate electrode 5, and surface electrode 6 of an aluminum silicon film and such a metal film on interlayer insulator film 7. On the front surface side of FZ-N substrate 1, p+-type base layer 2 is formed and n+-type emitter layer 3 is formed in p+-type base layer 2. On the back surface side of FZ-N substrate 1, p+-type collector layer 8 is formed and back surface electrode 9 is formed by laminating several kinds of metal films on p+-type collector layer 8.
In NPT-type IGBT 100 having the structure as described above, a shallow p+-type collector, the dose amount thereof is low, is used for p+-type collector layer 8. Since NPT-type IGBT 100 does not employ any p+-type epitaxial substrate, the total thickness of NPT-type IGBT 100 is much thinner than the total thickness of the PT-type IGBT described above.
Since the NPT structure facilitates controlling the hole injection rate, it is possible for the NPT structure to conduct high-speed switching without controlling the carrier lifetime. However, the ON-voltage of the NPT structure is rather high, since the ON-voltage depends on the thickness and resistivity of the n-type active layer. Since an FZ substrate is used in substitution for the p+-type epitaxial substrate, the chip costs can be reduced.
FIG. 12 is a cross sectional view of an FS-type IGBT. In FIG. 12, the same reference numerals as used in FIG. 11 are used to designate the same constituent elements and their duplicated descriptions are omitted for the sake of simplicity. In the same manner as NPT-type IGBT 100 described above, FS-type IGBT 200 shown in FIG. 12 employs FZ-N substrate 1 in substitution for the p+-type epitaxial substrate. The total thickness of FS-type IGBT 200 is from 100 μm to 200 μm. Corresponding to the breakdown voltage of 600 V, the n-type active layer is set to be around 70 μm in thickness, thin enough to be depleted. For depleting the n-type active layer, n+-type layer (n+-type buffer layer) 10 is formed on the back surface of FZ-N substrate 1 in FS-type IGBT 200. On n+-type buffer layer 10, p+-type collector layer 8 and back surface electrode 9 are formed. In other words, a continuous layer structure, in which a p-type layer and an n-type layer are continuous to each other, is formed on the back surface side of FZ-N substrate 1. It is not necessary for FS-type IGBT 200 to conduct lifetime control in the same manner as NPT-type IGBT 100.
For reducing the ON-voltage, an IGBT that combines a trench structure and an FS structure (hereinafter referred to as a “trench-FS IGBT”) has been developed. The trench-FS IGBT includes a narrow and deep trench formed in the surface portion thereof and a MOS gate formed on the side face of the trench. Recently, the total thickness of the trench-FS IGBT has been reduced by optimizing the design thereof.
Now the manufacturing method for manufacturing an IGBT will be described below in connection with the manufacture of FS-type IGBT 200 shown in FIG. 12 and with reference to FIGS. 13 through 17. FIG. 13 is a cross sectional view describing the state after the end of the process on the front surface side of FZ-N substrate 1. FIG. 14 is a cross sectional view describing the process of polishing FZ-N substrate 1. FIG. 15 is a cross sectional view describing the process of implanting ions to the back surface of FZ-N substrate 1. FIG. 16 is a cross sectional view describing the process of annealing the back surface of FZ-N substrate 1. FIG. 17 is a cross sectional view describing the process of forming a back surface electrode film on FZ-N substrate 1. In FIGS. 13 through 17, the same reference numerals as used in FIGS. 11 and 12 are used to designate the same constituent elements and their duplicated descriptions are omitted for the sake of simplicity.
The manufacture of FS-type IGBT 200 may be divided roughly into a front-surface-side process and a back-surface-side process. Now the front-surface-side process will be described below with reference to FIG. 13. First, SiO2 and polysilicon are deposited on the front surface of FZ-N substrate 1, windows are opened through the deposited SiO2 and polysilicon, and gate oxide film 4 and gate electrode 5 are formed. Then, BPSG is deposited, a window is opened through the deposited BPSG, and interlayer insulator film 7 is formed. Thus, an insulated gate structure is formed on the front surface of FZ-N substrate 1.
Then, p+-type base layer 2 is formed on the front surface side of FZ-N substrate 1 and n+-type emitter layer 3 is formed in p+-type base layer 2. Surface electrode 6 that will work for an emitter electrode is formed by depositing an aluminum silicon film such that the aluminum silicon film is in contact with n+-type emitter layer 3. Then, the aluminum silicon film is treated thermally at a low temperature between 400° C. and 500° C. to realize stable adhesiveness and low resistance wiring.
Although not shown in FIGS. 12 and 13, an insulating protector film is formed by employing polyimide and such an insulator on surface electrode 6 such that the insulating protector film is covering surface electrode 6. Now the back surface side process will be described below with reference to FIGS. 14 through 17. First, FZ-N substrate 1 is thinned to the desired thickness as shown in FIG. 14 by the polishing technique such as back grinding and etching applied to the back surface side thereof.
Then, phosphorus ions (P+) and, then, boron ions (B+) are implanted into the back surface side of FZ-N substrate 1 to form n+-type layer 10a and p+-type layer 8a as shown in FIG. 15. Then, FZ-N substrate 1 is thermally treated (annealed) in an electric furnace at a low temperature between 350° C. and 500° C. The heat treatment activates n+-type layer 10a, into which phosphorus ions are implanted, and p+-type layer 8a, into which boron ions are implanted, to form n+-type buffer layer 10 and p+-type collector layer 8 on the back surface side of FZ-N substrate 1. After implanting the boron ions, a surface contact layer (p-type layer) may be formed with no problem by implanting BF2 in the lowermost surface portion of p+-type collector layer 8, that will be in contact with the back surface electrode, for securing an ohmic contact with the back surface electrode.
In manufacturing NPT-type MOSFET 100 shown in FIG. 11, phosphorus ions (P+) are not implanted but boron ions (B+) are implanted into the back surface side of FZ-N substrate 1 in FIG. 15 solely to form p+-type layer 8a. Then, FZ-N substrate 1 is treated thermally in an electric furnace at a low temperature between 350° C. and 500° C. The heat treatment activates p+-type layer 8a, into which boron ions are implanted, to form p+-type collector layer 8 on the back surface side of FZ-N substrate 1.
Then, back surface electrode 9, formed of a metal film combination including an aluminum film, a titanium film, a nickel film and a gold film, is formed on p+-type collector layer 8. Finally, FZ-N substrate 1 is diced into chips, an aluminum wire electrode is fixed to the surface of surface electrode 6 by an ultrasonic wire bonding apparatus, and back surface electrode 9 is connected to a predetermined fixing stuff via a solder layer.
Recently, a matrix converter, which conducts a direct AC to AC conversion without interposing any DC between the AC and AC, has been attracting much attention. The matrix converter is different from the conventional converter in that the matrix converter does not need any capacitor. The matrix converter is advantageous, since the power supply higher harmonics are reduced. However, since the input to the matrix converter is an AC, it is required for the semiconductor switch to exhibit a certain reverse withstand voltage. If a conventional IGBT is used, it will be necessary to connect diodes for reverse blocking in series to each other.
FIG. 18 is a cross sectional view of a reverse blocking IGBT. In FIG. 18, the same reference numerals as used in FIG. 11 are used to designate the same constituent elements and their duplicated descriptions are omitted for the sake of simplicity. As shown in FIG. 18, reverse blocking IGBT 300 succeeds the fundamental properties of the conventional IGBT. Moreover, reverse blocking IGBT 300 is made to exhibits a reverse withstand voltage by pt-type isolation layer 11 formed therein. Since it is unnecessary to provide reverse blocking IGBT 300 having the structure described above with a series connection of diodes, the conduction loss may be halved and the conversion efficiency of a matrix converter may be improved greatly. If a technique for forming a deep junction, 100 μm or deeper, and a manufacturing technique for manufacturing an extremely thin wafer, 100 μm or thinner, are combined, it will be possible to manufacture a reverse blocking IGBT that exhibits excellent performances.
If the wafer thickness is reduced, the wafer rigidity will be impaired greatly. After the wafer is thinned, the wafer may not be so strong enough as to be held with an arm or with a jig in the subsequent manufacturing steps or in the subsequent transfer steps. For obviating the problem described above, a rib wafer having a rib structure on the back surface side thereof has been proposed (cf. the following Japanese Patent Publication No. 3620528 and Japanese Unexamined Patent Application Publication No. 2004-253527). On the back surface side of the rib wafer, the edge area of the wafer is thicker than the central area thereof. By employing the rib structure, the strength of the wafer is improved greatly and the cracking and parting of the wafer are reduced in handling the wafer during the transport steps thereof.
However, many other technical problems are posed on manufacturing an IGBT. For example, for obtaining an extremely thin IGBT of around 70 μm thick, it is necessary to conduct back surface grinding from the back surface side of the wafer, to conduct ion implantation from the back surface side of the wafer, and to thermally treat the back surface side of the wafer. During the treatments described above, bending may be caused in the wafer.
Various techniques have been investigated so far for activating the p-type impurity layer (p-type layer) and the n-type impurity layer (n-type layer) in the IGBT and such semiconductor devices. The activation techniques are indispensable for forming various semiconductor devices including the IGBT. In addition to the activation technique that employs an electric furnace as described above, activation techniques that anneal an impurity layer with a laser to activate the impurity layer have been developed. For example, a wafer is fixed to a supporting base board with an adhesive sheet for preventing the wafer from cracking and parting and a laser beam is irradiated to the wafer to activate the p-type layer and the n-type layer (cf. the following Japanese Unexamined Patent Application Publication No. 2004-140101). One of the techniques investigated employs the second higher harmonics of an yttrium aluminum garnet laser (hereinafter referred to as a “YAG 2ω laser”) and the other one of the techniques investigated employs the third higher harmonics of a YAG laser (hereinafter referred to as a “YAG 3ω laser”) for the activation (cf. the following Japanese Unexamined Patent Application Publication No. 2003-059856 and Japanese Unexamined Patent Application Publication No. 2005-223301).
For the laser annealing techniques, it has been proposed to activate the impurities in the regions, the depths thereof from the substrate surface are different, by irradiating laser beams, the pulse widths thereof or the energy densities thereof are different from each other (cf. the following Japanese Patent Publication No. 4043865).
The lasers are used for the treatments other than the laser annealing for activating the impurities. For example, the lasers are used for removing a surface protector film formed on a metal electrode film by laser abrasion to bore an opening through the surface protector film for leading out an electrode terminal and for applying a cleaning treatment including plasma ashing to the surface of the opening bored (cf. the following Japanese Unexamined Patent Application Publication No. 2004-273771).
An apparatus has been proposed for judging, under the vacuum as well as not under the vacuum, whether the cleaning of a substrate surface using a laser is finished or not (cf. the following Japanese Unexamined Patent Application Publication No. 2002-043269).
However, it is impossible for the conventional annealing in an electric furnace to highly activate the p-type layer. When it is necessary to conduct annealing in an electric furnace at 300° C. or higher, the technique that uses an adhesive sheet to prevent wafer cracking from causing is unemployable, since the adhesive sheet is resistive against heat usually at 200° C. or lower.
When the p-type and n-type layers are activated by laser annealing in place of electric furnace annealing, a laser beam is irradiated with a high energy density from the back surface side of a thin wafer that subjected to the front-surface-side process and the back grinding. Due to this, the temperature of the surface opposite to the surface irradiated with a laser beam, that is the front surface, on which a gate structure is formed through the front-surface-side process, becomes high. In detail, when the wafer is 70 μm thick, the temperature on the front wafer surface may rise to about 500° C. As the temperature on the front wafer surface rises to 500° C., the surface electrode and the insulating protector film on the surface electrode will melt and the device will be broken down.
When laser annealing is conduced with a single pulse, it will be necessary to conduct irradiation for a long time and it will take several hr. to anneal a sheet of wafer. Machining traces will be caused sometimes in the wafer surface by laser irradiation, since a laser beam, the irradiation energy density thereof is high, is irradiated.
FIGS. 19 and 20 are cross sectional views of a wafer for explaining the problems caused by the conventional laser annealing. As shown in FIG. 19, particles 20 such as dusts may be on the back surface of a wafer (e.g. FZ-N substrate 1) sometimes. When a shallow p-type layer and a shallow n-type layer, about 1 μm deep from the back surface of wafer 1, are activated by laser annealing, region 21, on which particle 20 is, is not irradiated with a laser beam and the impurity in region 21 is not activated. If the p-type and n-type layer are not formed normally, a large leakage current will be caused, the contact resistance of the electrode formed on the back surface of the wafer will be large and such detects will be caused in the device.
In view of the foregoing, it would be desirable to obviate the problems described above. It would be also desirable to provide a method for manufacturing a semiconductor device that facilitates preventing nonuniform laser irradiation from causing during laser annealing and preventing defective devices from causing.